--- title: "Instruction Set Architecture as a Contract" description: "An instruction set architecture specifies instruction encodings and behaviour, visible registers and addressing rules. Different implementations can preserve that interface while changing scheduling, " canonical: https://lightmysky.com/learn/computing/instruction-set-architecture-as-a-contract-mt_pbwHRePY5M source: https://lightmysky.com/learn/computing/instruction-set-architecture-as-a-contract-mt_pbwHRePY5M.md retrieved: 2026-11-12 --- > **Agent view.** This is the Markdown twin of the page, for tools and assistants. > When to use this site, and the call that answers each job: https://lightmysky.com/agent-instructions.md > API description (OpenAPI 3.1): https://lightmysky.com/openapi.json · Authentication: https://lightmysky.com/auth.md > Pricing: https://lightmysky.com/pricing.md · Catalog: https://lightmysky.com/llms.txt · Full catalog: https://lightmysky.com/llms-full.txt > Every machine-readable file on this domain: https://lightmysky.com/.well-known/ai-catalog.json > Ask for Markdown with `Accept: text/markdown`, a `.md` address, or `?mode=agent`. # Instruction Set Architecture as a Contract An instruction set architecture specifies instruction encodings and behaviour, visible registers and addressing rules. Different implementations can preserve that interface while changing scheduling, pipelines, caches or internal registers. Running an application also requires its software environment. Subject: Computing · Area: Computer Systems · Ages 18 to 19 Page: https://lightmysky.com/learn/computing/instruction-set-architecture-as-a-contract-mt_pbwHRePY5M ## Ready when they can - Name what an instruction set fixes and what it deliberately leaves to the implementation - Compare a load-store design with one that operates directly on memory by instruction count and memory accesses - Explain why two chips with different internals can run the same binary ## Lesson: The promise between chips and programs The assembly listings use an instruction set architecture (ISA): instruction encodings and behaviour, visible registers and addressing rules. A change preserves this interface only if these rules still hold. Removing a register or operation used by an old binary breaks its support; internal scheduling may change if ISA behaviour is preserved. Clock speed, cache size and circuit design are implementation choices, not generally fixed performance promises. *(drawing: In this load-store model, LOAD reads data memory, ADD uses registers, and STORE writes data memory.)* The ISA's programmer-visible interface specifies instruction encodings and behaviour, visible registers and addressing rules. Two chips can execute a binary when its required ISA features and execution mode are supported. An application also needs its required operating system and libraries. Different internal designs can preserve those requirements while producing different timing. ISA compatibility alone does not promise every application will run. **Example.** Recall x = x + 1 from the earlier assembly lesson. Model A uses LOAD R,[x]; ADD R,#1; STORE [x],R. Model B defines ADDMEM [x],#1 to read x, add 1 and write x in one instruction. A uses 3 instructions; B uses 1 combining three actions. B still accesses memory. This comparison applies to these models; it is not a universal rule about hardware cost or speed. Changing internal scheduling can preserve a binary's required instruction behaviour, mode and software support. When all remain supported, recompilation is not needed merely because scheduling changed. Timing may differ. This is a compatibility check: identify the changed feature, then check whether any required interface or software support was removed. **Example.** Compiled instructions select registers using encoded numbers. Suppose selector 2 names ISA register 2. Calling it 'total' in assembly documentation does not change that encoding. Removing register 2, or making selector 2 mean something different, changes the interface. An old binary still contains the old selector; it does not automatically learn the new mapping. ISA-visible registers differ from internal physical registers. Extra physical registers can hold temporary copies without adding registers to the ISA. A pipeline overlaps stages of different instructions; changing its depth is another internal choice. To assess an old binary, separate these internal counts from the encoded registers and instruction meanings it uses. Then check the required mode and software support. **Recap.** Preserve instruction encodings and behaviour, visible registers and addressing rules. Internal designs and timing may differ. Applications also need their required software support. *Lesson, questions and flashcards written for this dataset.* ## Practice 8 questions on this page, each with its working shown. ## Needs first - [Assembly Language and the Instruction Set](https://lightmysky.com/learn/computing/assembly-language-and-the-instruction-set-mt_bzmsfvdzwp) - [Registers, Buses and the Fetch-Execute Cycle in Detail](https://lightmysky.com/learn/computing/registers-buses-and-the-fetch-execute-cycle-in-detail-mt_yjy3eSStzH) ## Opens up - [Code Generation and What an Optimiser May Change](https://lightmysky.com/learn/computing/code-generation-and-what-an-optimiser-may-change-mt__ZSPwP4hfA) - [The Memory Hierarchy and Why Caching Works](https://lightmysky.com/learn/computing/the-memory-hierarchy-and-why-caching-works-mt_0f5ArFPlxP) - [What an Operating System Is: Privilege and System Calls](https://lightmysky.com/learn/computing/what-an-operating-system-is-privilege-and-system-calls-mt_0kMavEKxpX) - [Race Conditions and Mutual Exclusion](https://lightmysky.com/learn/computing/race-conditions-and-mutual-exclusion-mt_hygT74jJDE)