Pipelining and the Cost of a Hazard · seed 1 · A4, ink-friendly. The answer key prints on its own page for grown-ups.
به انگلیسی

Overlapping work without rushing it

Computing · Computer Systems · ages 18-20
Name ______________________   Date ____________

  1. A pipeline uses the stage sequence fetch, decode, execute, memory, write back. An instruction visits every stage. How many stages does it visit?

    • One stage
    • Five stages
    • Nine stages

  2. In our ideal same-clock model, which quantity does instruction overlap increase?

    • Completed instructions per cycle
    • Stages visited by each instruction
    • Cycles spent by each instruction

  3. An add result is ready after execute. If it reaches the next instruction in time, forwarding can supply it before register write-back.

    Circle one:   True   False

  4. A following add needs a load result before that result is available. Even forwarding cannot deliver it in time. What must the add do?

    • Use the register's earlier value instead
    • Finish before either input is available
    • Wait until the needed value is available

  5. An empty five-stage pipeline starts one instruction per cycle. Each stage takes one cycle and there are no stalls. How many cycles are needed to complete five instructions?

    Answer: ______________

  6. A branch prediction selected the incorrect path. What happens to younger instructions fetched from that path?

    • They are discarded and fetching redirects
    • They complete and replace the correct path
    • They are retained as valid program results

  7. Discarding wrong-path instructions after a branch misprediction guarantees that every cache effect of those instructions is also undone.

    Circle one:   True   False

  8. An empty five-stage pipeline starts one instruction per cycle. Stages take one cycle. Eight instructions would take 12 cycles without stalls. Two stall cycles are added. What is the total?

    • 12 cycles, because stalls overlap all useful work
    • 14 cycles, from the base total plus two stalls
    • 16 cycles, because each stall is counted twice
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Answer key

For grown-ups. Fold this page away before handing over the rest.

Overlapping work without rushing it W1-mt_GI_fPY9d6s-s1

  1. Five stages · Each instruction visits fetch, decode, execute, memory and write back: five stages.
  2. Completed instructions per cycle · Overlap lets more instructions finish per cycle. This is higher throughput, not a shorter trip for each instruction.
  3. True · Forwarding uses an available result without waiting for register write-back, provided the consumer receives it in time.
  4. Wait until the needed value is available · Forwarding cannot supply a result that does not yet exist. The add must wait for its input.
  5. 9 · The first instruction takes five cycles. Four followers add four more: 5 + 4 = 9.
  6. They are discarded and fetching redirects · Younger wrong-path instructions are discarded. Fetching redirects to the path selected by the resolved branch.
  7. False · Discarded instructions must not provide architectural program results, but some cache effects may remain.
  8. 14 cycles, from the base total plus two stalls · The model adds each stall cycle once: 12 + 2 = 14 cycles.
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