Registers, Buses and the Fetch-Execute Cycle in Detail · seed 1 · A4, ink-friendly. The answer key prints on its own page for grown-ups.
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One instruction's journey through the CPU

Computing · Computer Systems · ages 16-18
Name ______________________   Date ____________

  1. In this model, PC=18 just before fetch. What does 18 identify?

    • the running result of the last addition
    • the address of the next instruction
    • the control signal for the next bus read

  2. In this lesson's cycle model, what order takes an instruction from memory to its action?

    • fetch, decode, execute
    • execute, fetch, decode
    • decode, execute, fetch

  3. In this model, an address goes to memory on the address bus, and the fetched instruction returns on the data bus.

    Circle one:   True   False

  4. In this model, the accumulator holds 6 and memory location 92 holds 3. ADD [92] executes. Where is the result?

    • accumulator holds 9
    • program counter holds 9
    • data register holds 9

  5. In this model, PC=24 and memory location 24 holds ADD [70]. During instruction fetch, which register pairing is correct?

    • accumulator holds 24; program counter receives ADD [70]
    • data register holds 24; address register receives ADD [70]
    • address register holds 24; data register receives ADD [70]

  6. In this lesson's model, fetch leaves PC=25. The unconditional instruction JUMP [64] then runs. What happens?

    • execute sets PC=64, so the next fetch reads address 64
    • fetch sets PC=0, so the next fetch reads address zero
    • decode swaps PC with the accumulator before the jump

  7. In this model, fetch leaves PC=31. BLT [90] has a greater comparison flag. A trace writes PC=90 during decode. What should the trace show instead?

    • PC becomes 90; decode takes the branch
    • PC becomes 90; execute takes the branch
    • PC stays 31; the greater flag makes BLT not taken

  8. A model machine widens its address bus from 4 bits to 8 bits. Its data bus stays 8 bits wide. What are the new potential address count and data-transfer size?

    • 32 possible addresses; 16 data bits per transfer
    • 256 possible addresses; 8 data bits per transfer
    • 16 possible addresses; 16 data bits per transfer
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Answer key

For grown-ups. Fold this page away before handing over the rest.

One instruction's journey through the CPU W1-mt_yjy3eSStzH-s1

  1. the address of the next instruction · PC contains an instruction address. PC=18 tells fetch to read the instruction at memory location 18.
  2. fetch, decode, execute · Fetch obtains the instruction, decode identifies its operation, and execute carries it out.
  3. True · The address bus selects the memory location. The data bus carries its returned contents, including an instruction.
  4. accumulator holds 9 · Execute fetches operand 3 from location 92. The ALU adds 6+3 and writes result 9 into the accumulator.
  5. address register holds 24; data register receives ADD [70] · Fetch copies PC's address 24 into the address register. Memory returns ADD [70] into the data register.
  6. execute sets PC=64, so the next fetch reads address 64 · An unconditional JUMP is taken. In this model, execute writes target 64 into PC, replacing 25.
  7. PC stays 31; the greater flag makes BLT not taken · Decode does not take a branch in this model. BLT also fails on greater, so execute leaves the incremented PC=31 unchanged.
  8. 256 possible addresses; 8 data bits per transfer · Eight address bits encode 2^8=256 addresses. The unchanged 8-bit data bus still moves 8 bits per transfer.
Worksheet · LightMySky