Assembly Language and the Instruction Set
Assembly uses readable names for operations in a processor's instruction set. Trace registers, memory and branch decisions in a stated instruction model, and compare a high-level statement with its possible machine instructions.
What a learner can do afterwards
- Hand-run a short assembly listing and give the final register and memory contents
- Write a counting loop using compare and branch instructions
- Translate one line of high-level code into the instructions it needs
1 · Read
The adders you studied can perform ADD's arithmetic; registers hold its result and any register inputs. Assembly names machine operations. An assembler turns it into machine code. A directive tells the assembler how to build a file. A pseudo-instruction is shorthand that may expand into machine instructions. A label names a position. In our teaching model, ADD R,#3 adds literal 3 to R; ADD T,C adds C to T. # marks a literal. HALT stops execution.
Registers are small, fast storage locations inside the processor. Our model names two of them T and C. MOV T,#0 puts literal 0 in T. Changing T does not automatically change a memory cell: a store instruction is needed. A register holds a bit pattern, not an entire program.
In this model, CMP sets a flag to less, equal or greater without changing its operands. BLT jumps if the flag is less; BLE jumps if it is less or equal. Otherwise execution continues. To add 1 through 3, run the listing below. The loop adds C to T before increasing C. CMP C,#4 then decides whether to repeat. The final values are T=6 and C=4.
Hand-run one instruction at a time from the current state. If T=4 and C=2, ADD T,C changes T to 6 and leaves C at 2. ADD C,#1 then changes C to 3 and leaves T at 6. Record each change before reading the next instruction. Follow a jump to its target rather than continuing down the page.
An instruction set architecture (ISA) defines supported operations, registers and addressing rules. Our model's LOAD R,[x] reads memory into R; STORE [x],R writes it back. One translation of x = x + 1 is LOAD R,[x]; ADD R,#1; STORE [x],R. Other ISAs allow memory arithmetic. A compiler may keep values in registers or remove unused work, so one statement can become zero, one or several instructions.
Check a loop's exit test against its update order. If the counter increases after the addition, the comparison sees the next value to add. BLT with limit L repeats only when C is below L. BLE with limit L also repeats when C equals L. Trace the last two passes to check whether the intended final value is included.
A flag-dependent branch uses the recorded comparison. With C=4, CMP C,#4 sets equal: BLT does not jump, but BLE does. With C=3, CMP C,#4 sets less, so BLT jumps. Comparison leaves C unchanged. Track the flag and resulting instruction path along with any changed registers or memory.
Use the stated instruction rules. Update the trace after each instruction, follow branch decisions, and check a loop's final pass.
Lesson, questions and flashcards written for this dataset using a stated teaching instruction model.
Readings written for this dataset. Video references are credited to their Khan Academy source records. Video licenses are not specified.
2 · Watch
به انگلیسیTake it off screen
Where it sits
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Optional connections
8 questions wait behind this lesson, each with its answer explained. Every answer feeds the sky: stars light as they are learned, and dim when it is time to come back.