Virtual Memory and Address Translation
A process normally uses virtual addresses. Hardware translates them using page mappings and permissions, often cached in a TLB. The OS controls isolation and intentional sharing. With backing storage, valid pages need not all occupy RAM at once.
What a learner can do afterwards
- Translate a virtual address to a physical one given a page table and page size
- Explain what the translation lookaside buffer caches and why it matters
- Say what isolation the page table gives and what it does not
1 · Read
A process's virtual address space is its set of virtual addresses. An address can belong to that space without being mapped or permitted for a particular access. Separate processes can use the same virtual number for different physical locations. The OS also controls intentional sharing.
For page size S, divide a virtual address by S: the whole-number quotient is its page number and the remainder is its offset. Look up the page's frame. Physical address = frame number times S plus offset. In a toy system with S = 100, address 340 is page 3, offset 40. If page 3 maps to frame 7, its physical address is 740. The same method works for other page sizes.
Each CPU access using a virtual address needs translation and permission checks. A translation lookaside buffer, or TLB, caches page-to-frame mappings and related permissions. On a hit, hardware can use that cached translation without a page-table walk. It does not cache the page's data bytes.
The OS chooses mappings and permissions so a process cannot access another process's private memory through ordinary user-mode loads and stores. Separate tables can also map an intentionally shared page to the same physical frame. If both processes have write permission, either can change that shared data.
An unmapped address has no valid mapping, so access is rejected. A read-only page's permissions reject writes. These checks do not prove that a permitted write is logically correct. A program can overwrite its own writable data with an unintended value while all translation and permission checks work as designed.
Virtual memory does not require every valid virtual page to be in RAM at once. With backing storage, the OS can keep some page contents elsewhere and load them when needed. Access to a valid nonresident page causes a page fault. The OS handles it and may retry the access after loading the page; invalid accesses may instead be rejected.
Translate the page number and keep the offset. Mappings and permissions control access; TLBs cache translations, and valid pages need not all be resident.
Original lesson, questions and flashcards about virtual addresses, mappings and permissions.
Original reading and flashcards about memory mappings, sharing and resident pages.
2 · Watch
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Where it sits
8 questions wait behind this lesson, each with its answer explained. Every answer feeds the sky: stars light as they are learned, and dim when it is time to come back.