Registers, Buses and the Fetch-Execute Cycle in Detail
Trace an instruction through a stated accumulator-machine model, naming registers and the address, data and control buses. A taken branch writes its target into the program counter; a branch that is not taken leaves the next sequential address in place.
What a learner can do afterwards
- Walk one instruction through the cycle, naming the register holding each value at each step
- Explain how a taken or untaken branch affects the program counter in the stated cycle model
- Explain what a wider address bus or data bus changes about the machine
1 · Read
A memory address is the number of a memory location. The program counter (PC) holds the next instruction's address. Our model stores each instruction in one memory word, so fetch increases PC by 1 after using its old address. Unlike the earlier ADD T,C model, ADD [n] here adds memory location n's value to the accumulator. Real processors can use different registers and instruction lengths.
Fetch ADD [80] from address 40. Copy PC=40 into the address register, which sends 40 on the address bus. A READ signal uses the control bus. Memory returns the instruction on the data bus into the data register. Copy it into the instruction register and increase PC to 41. The instruction register holds it for decode. The data bus carries instructions as well as operand values.
Decode reads ADD [80] in the instruction register. During execute, put operand address 80 in the address register and send it on the address bus with READ on the control bus. Memory value 5 returns on the data bus into the data register. The arithmetic logic unit (ALU) adds it to accumulator value 7, then writes 12 into the accumulator. PC stays 41.
In this model, a taken branch writes its target into PC during execute. For branches, brackets enclose the target address itself. An unconditional JUMP is always taken. BLT is taken only when the comparison flag is less. After fetch leaves PC=41, JUMP [60] sets PC=60 during execute. An untaken conditional branch leaves the incremented PC unchanged. Control-bus signals include read, write and clock timing.
With n address bits, 2^n different addresses can be encoded. More address lines increase that potential range, not necessarily the installed memory. For example, 3 bits encode 8 addresses and 4 bits encode 16. Data-bus width is the number of bits moved per transfer: widening it increases that chunk. Neither change alone specifies clock speed.
Audit a conditional-branch trace in order. First note the PC left by fetch. Decode identifies the operation and target; it does not take the branch in this model. At execute, check the comparison flag. BLT passes only on less, not on equal or greater. If it passes, write the target into PC. Otherwise retain the PC already recorded after fetch.
In this model, fetch fills the instruction register, execute can fetch an operand, and the accumulator holds the add result. Only a taken branch replaces the next sequential PC.
Lesson, questions and flashcards written for this dataset using a stated accumulator-machine model.
Additional readings and flashcards written for this dataset. Linked video from Khan Academy and Code.org.
2 · Watch
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Optional connections
8 questions wait behind this lesson, each with its answer explained. Every answer feeds the sky: stars light as they are learned, and dim when it is time to come back.