Many Cores and the Limit on Speedup
For a fixed workload with unchanged serial time, Amdahl's ideal model gives speedup 1 / (s + (1 - s) / N), where s is the serial fraction and N is the core count. For positive s, 1 / s is the limiting bound. Coordination and resource contention can reduce gains.
What a learner can do afterwards
- Compute ideal finite-core speedup and the limiting bound for a fixed workload that is one tenth serial
- Distinguish work that splits across cores from work that splits across data lanes
- Explain why adding cores can make a program slower
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Pipelining overlaps stages inside a core; multiple cores can share a program's work. In Amdahl's model, the workload stays fixed and the serial part takes the same time. If its positive fraction is s, speedup approaches the bound 1 / s as core count grows. A serial tenth gives a tenfold bound, not tenfold speedup at every count.
Normalize the one-core time to 1. For N cores, ideal time is s + (1 - s) / N; speedup is 1 divided by that time. This assumes equal sharing of the parallel part and no added overhead. With s = 0.25 and N = 3, time is 0.25 + 0.75 / 3 = 0.5, so speedup is 2.
Multiple cores can execute different instruction streams. SIMD data lanes apply the same operation to several data elements together. Both can be used by one program: several cores might each perform SIMD additions. Lanes do not turn the serial part of a fixed workload into independent tasks.
Actual time includes overhead that the ideal formula leaves out. Dividing work, coordinating results and waiting for shared resources all take time. A lock allows controlled access to a shared resource; workers may have to wait for it. If these costs exceed the time saved by parallel work, more cores can make the program slower.
For a serial tenth on 100 cores, ideal time is 0.1 + 0.9 / 100 = 0.109. Speedup is 1 / 0.109, about 9.17. This is below ten because the parallel part still takes some time. Increasing N reduces that part, but leaves the serial 0.1 unchanged.
For fixed work, unchanged serial time limits ideal speedup. Compute finite-core time before inverting it. Cores and SIMD lanes differ; overhead can erase the gain.
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